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? semiconductor components industries, llc, 2006 march, 2006 -- rev. 11 1 publication order number: ncv8800/d ncv8800 series synchronous buck regulator with 1.0 amp switch the ncv8800 is an automotive synchronous step--down buck regulator. this part provides an efficient step--down voltage compared to linear regulators. the ncv8800 uses very few external components allowing for maximum use of p rinted circuit board space. features ? output voltage options: 2.6 v, 3.3 v, 5.0 v, 7.5 v ? 3.0% output ? 3.5 v operation ? auxiliary hold up pin (for cranking conditions) ? on--chip switching power devices (0.4 ? r ds(on) ) ? constant frequency ? synchronous operation ? on--chip charge pump control circuitry ? nonoverlap logic ? power up sequencing control option (2.6 v and 3.3 v only) ? enable battery voltage capable option ? selectable reset delay ? dual pin feedback connection ? v 2 ? control topology ? internally fused leads in so--16l package ? ncv prefix for automotive and other applications requiring site and change control ? these devices are available in pb--free package(s). specifications herein apply to both standard and pb--free devices. please see our website at www.onsemi.com for specific pb--free orderable part numbers, or contact your local on semiconductor sales office or representative. typical applications ? telecommunications ? mobile multimedia ? instrumentation ? automotive entertainment systems so--16l dw suffix case 751g 1 16 ncv8800xy awlyyww comp fb2 1 16 nc fb1 v in2 delay gnd gnd gnd gnd switch reset cp enable v in auxiliary pin connections and marking diagram x = voltage ratings as indicated below: 2=2.6v 3=3.3v 5=5.0v 7=7.5v y = enable option as indicated below: s = sequenced h = high voltage a = assembly location wl, l = wafer lot yy, y = year ww, w = work week see detailed ordering and shipping information in the package dimensions section on page 12 of this data sheet. ordering information http://onsemi.com
ncv8800 series http://onsemi.com 2 10 20 30 40 50 60 70 80 90 100 0 100 200 300 400 500 600 700 800 load current (ma) efficiency (%) figure 1. efficiency vs. load current v out =7.5v v out =5.0v v out =3.3v v out =2.6v v in = 13.5 v l =100 m h 0
ncv8800 series http://onsemi.com 3 figure 2. application diagram auxiliary enable reset gnd gnd delay fb1 fb2 v in cp switch gnd gnd v in2 nc comp ncv8800 5.1 k reset 0.1 f 100 f 100 h 0.01 f v bat v out external regulator auxiliary supply (optional) 0.1 f 1.0 k 10 f* *the supply capacitor must be located physically close to the ic pins. 100 ? 0.01 f mra4004t3 figure 3. typical operation with an 8.0 ? load
ncv8800 series http://onsemi.com 4 maximum ratings* rating value unit supply voltages, v in ,v in2 --0.3to45 v auxiliary --0.3to8.0 v enable (sequenced option) --0.3to7.0 v enable (high voltage option) --0.3to8.0 v reset --0.3to30 v delay --0.3to7.0 v switch (v 5vsense =0v) --1.0to45 v operating junction temperature --40 to 150 c storage temperature range --55 to 150 c esd -- human body model (auxiliary, enable, reset ,delay,fb1,fb2,cp,switch,comp) human body model (vin, vin2) machine model (all pins) 2.0 1.3 200 kv kv v package thermal resistance, so--16l junction--to--case, r jc junction--to--ambient, r ja 18 80 c/w lead temperature soldering: reflow (smd style only) (note 1) 240 peak (note 2) c 1. 60 second maximum above 183 c. 2. --5 c/+0 c allowable condition. *the maximum package power dissipation must be observed.
ncv8800 series http://onsemi.com 5 electrical characteristics (--40 c t j 125 c; sequenced enable option: 3.5 v v in 16 v, 3.5 v v in2 16 v, auxiliary = 6.0 v, enable = 5.0 v; high voltage enable option: 6.0 v v in 16 v, 6.0 v v in2 16 v; unless otherwise stated.) characteristic test conditions min typ max unit general quiescent current (v in2 ) sleep mode operating enable = 0 v, v in = 12.6 v, t j =--40 c enable = 0 v, v in = 12.6 v, t j =25 c, 125 c enable = 5.0 v, v in = 13.5 v, i out =0 -- -- -- -- -- -- 40 30 15 a a ma switching frequency -- 180 200 230 khz switching duty cycle -- 85 90 95 % thermal shutdown note 3 150 165 200 c feedback feedback voltage threshold, 2.6 v option (v fb ) -- 2.522 2.6 2.678 v feedback voltage threshold, 3.3 v option (v fb ) -- 3.201 3.3 3.399 v feedback voltage threshold, 5.0 v option (v fb ) -- 4.850 5.0 5.150 v feedback voltage threshold, 7.5 v option (v fb ) -- 7.275 7.5 7.725 v reset undervoltage reset threshold, 2.6 v option v out increasing v out decreasing 2.44 2.40 -- -- v fb v fb -- 0.04 v v undervoltage reset hysteresis, 2.6 v option -- 40 -- -- mv overvoltage reset threshold, 2.6 v option v out increasing v out decreasing v fb +0.04 v fb -- -- 2.80 2.76 v v overvoltage reset hysteresis, 2.6 v option -- 40 -- -- mv undervoltage reset threshold, 3.3 v option v out increasing v out decreasing 3.10 3.04 -- -- v fb v fb -- 0.05 v v undervoltage reset hysteresis, 3.3 v option -- 50 -- -- mv overvoltage reset threshold, 3.3 v option v out increasing v out decreasing v fb +0.05 v fb -- -- 3.56 3.51 v v overvoltage reset hysteresis, 3.3 v option -- 50 -- -- mv undervoltage reset threshold, 5.0 v option v out increasing v out decreasing 4.70 4.61 -- -- v fb v fb -- 0.075 v v undervoltage reset hysteresis, 5.0 v option -- 75 -- -- mv overvoltage reset threshold, 5.0 v option v out increasing v out decreasing v fb + 0.075 v fb -- -- 5.39 5.31 v v overvoltage reset hysteresis, 5.0 v option -- 75 -- -- mv undervoltage reset threshold, 7.5 v option v out increasing v out decreasing 7.05 6.92 -- -- v fb v fb -- 0 . 1 1 5 v v undervoltage reset hysteresis, 7.5 v option -- 115 -- -- mv overvoltage reset threshold, 7.5 v option v out increasing v out decreasing v fb +0.115 v fb -- -- 8.08 7.96 v v overvoltage reset hysteresis, 7.5 v option -- 115 -- -- mv 3. guaranteed by design.
ncv8800 series http://onsemi.com 6 electrical characteristics (continued) (--40 c t j 125 c; sequenced enable option: 3.5 v v in 16 v, 3.5 v v in2 16 v, auxiliary = 6.0 v, enable = 5.0 v; high voltage enable option: 6.0 v v in 16 v, 6.0 v v in2 16 v; unless otherwise stated.) characteristic test conditions min typ max unit reset reset leakage current reset =5.25v -- -- 25 a reset output low voltage i out =1.6ma -- -- 0.4 v reset delay delay connected to fb1, fb2 delay = 0 v 28.70 14.35 32.60 16.30 36.66 18.33 ms ms enable enable threshold increasing decreasing 1.1 1.0 1.9 1.6 2.3 2.2 v v enable hysteresis -- 100 250 550 mv enable input resistance enable = 5.25 v, v in2 = 13.5 v 50 100 200 k delay delay input current delay = 5.15 v 4.0 10 16 a switch switch on resistance i switch =0.5a,t j =--40 c, 25 c i switch =0.5a,t j = 125 c -- -- 0.40 0.55 0.60 0.75 ? ? current limit -- 1.0 1.6 2.5 a error amplifier error amplifier transconductance 2.6 v option 3.3 v option 5.0 v option 7.5 v option 2.58 v fb1 2.62 v 2.58 v fb2 2.62 v 3.275 v fb1 3.325 v 3.275 v fb2 3.325 v 4.962 v fb1 5.038 v 4.962 v fb2 5.038 v 7.442 v fb1 7.558 v 7.442 v fb2 7.558 v 0.55 0.43 0.28 0.19 -- -- -- -- 2.10 1.65 1.09 0.73 1/m ? error amplifier bandwidth note 4 1.0 -- -- mhz output tracking (sequencing) feedback to enable tracking voltage, 2.6 v option -- 60 67 75 % feedback to enable tracking voltage, 3.3 v option -- 80 85 90 % 4. guaranteed by design.
ncv8800 series http://onsemi.com 7 package pin description package lead # lead symbol function 1 auxiliary alternate path for voltage input to the ic. 2 enable sense for powerup. this pin must be high before switch turns on. 3 rese t cmos compatible open drain output lead. reset goes low whenever fb1 or fb2 is below the reset low threshold, or above the reset high threshold. 4, 5, 12, 13 gnd ground. 6 delay reset delay control. time is doubled when pin moved to fb1 or fb2 from 0 v. 7 fb1 voltage feedback to error amplifier. shorted with fb2. 8 fb2 voltage feedback to error amplifier. shorted with fb1. 9 comp loop compensation node for error amplifier. (1.0 k ? and 0.1 f to ground). 10 nc no connection. 11 v in2 supply input voltage for internal bias circuitry. 14 switch drive for external inductor. 15 cp node for charge pump bootstrap capacitor. 16 v in supply input voltage for output drivers.
ncv8800 series http://onsemi.com 8 figure 4. block diagram nonoverlap logic and drive r sq q latch 0.4 ? 0.4 ? switch ovlo current limit gnd uvlo 200 khz osc art ramp + error amp por timer -- -- + -- + reset cp control v in bandgap voltage reference 5.1 k 33 h 2.6 v v bat 0.01 f cp over/under voltage reset comp power up/down sequence and enable ovlo uvlo delay comp enable auxiliary fb1 fb2 pwm comp current limit 100 f v in2 bias thermal shutdown 0.1 m f 100 mra4004t3 1k 0.1 m f
ncv8800 series http://onsemi.com 9 circuit description enable the ncv8800 remains in sleep mode drawing less than 25 a of quiescent current until the enable pin is brought high powering up the device. there are two options available for the enable feature. ? option 1 (sequenced). the output voltage tracks the enable pin with a maximum delta voltage between them (reference the output tracking specs in the electrical characteristics). t his allows the device to be used with microprocessors requiring dual supply voltages. one voltage is typically needed to power the core of the microprocessor, and another high voltage is needed to power the microprocessor i/o. ? option 2 (high voltage). this option removes the sequencing feature above, and allows the device to be controlled up to the battery voltage on the enable pin with an external resistor (10 k). see figure 5. figure 5. switched battery application enable v in v bat 10 k auxiliary the auxiliary pin provides an alternate path for the ic to maintain operation. the auxiliary pin is diode or?d with the v in pin to the control circuitry (the dmos output drivers are not included). if the voltage (v in ) from the battery dips as low as 3.5 v during a crank condition, the ncv8800 will maintain operation through a 6.0 v(min) connection on the auxiliary pin. using this feature is optional. this pin should be grounded when not in use. v in normal supply voltage input. an external diode must be provided to afford reverse battery protection. switch dmos output drivers with 0.75 ? max push/pull capability. non--overlap logic is provided to guarantee s hoot through current is minimized. reset the reset is an open drain output which goes low when the feedback voltage on fb1 and fb2 goes below the undervoltage reset threshold. the output also goes low when the voltage on fb1 and fb2 exceeds the overvoltage reset threshold. the reset output is an open drain output capable of sinking 1.6 ma. fb1 and fb2 fb1 and fb2 are the feedback pins to the error amplifier, which control the output switch as needed to the regulated output. they are internally wire bonded to the same electrical connection providing double protection for an open circuit which would cause the buck regulator to rise above its desired output reaching the voltage on v in .these pins also provide the feedback path for the reset function. delay there are two options for the delay time for the reset to go low. connecting the pin to gnd will provide a minimum of 14 ms. connecting the pin to fb1 and fb2 will provide a minimum of 28 ms. absolute max voltage on the delay pin is 7.0 v. use a resistor divider to run off higher voltages. the 7.5 v option will require this divider (see figure 6). figure 6. delay (7.0 v max) v out comp the comp pin provides access to the error amplifiers output. switching power supplies work as feedback control systems, and require compensation for stability. a 1.0 k resistor and 0.1 f capacitor work well in the application in figure 2. cp the on--chip dmos drivers require the gates of the devices to be pulled above their drain voltage. an external capacitor located between the switch output, and the cp pin provides the charge pump action to drive the gate of the high--side driver high enough to turn the device on.
ncv8800 series http://onsemi.com 10 applications information v out ncv8800 switch fb2 r ex power up/down sequence and enable -- + r2 21.4 k error amp 1.20 v 56 a fb1 r1* figure 7. *the value of r1 is dependent on the output voltage option and is between 25 k and 200 k. increasing the output voltage adjustments to the output voltage can be made with an external resistor (r ex ). the increase in output voltage will typically be 56 a r ex . caution and consideration must be given to the tracking feature and temperature coefficient and matching of internal and external resistors. output tracking always follows the f eedback pins (fb1 and fb2). the typical temperature coefficient for r1 and r2 is +4600 ppm/ c. theory of operation v 2 control method the v 2 method of control uses a ramp signal that is generated by the esr of the output capacitors. this ramp is proportional to the ac current through the main inductor and is offset by the value of the dc output voltage. this control scheme inherently compensates for variations in either line or load conditions, since the ramp signal is generated from the output voltage itself. this control scheme differs from traditional techniques such as voltage mode, which generates an artificial ramp, and current mode, which generates a ramp from inductor current. ? + ? + ramp signal error signal error amplifier comp gate(l) gate(h) output voltage feedback pwm comparator figure 8. v 2 control block diagram reference voltage the v 2 control method is illustrated in figure 8. the output voltage is used to generate both the error signal and the ramp signal. since the ramp signal is simply the output voltage, it is affected by any change in the output regardless of the origin of the change. the ramp signal also contains the dc portion of the output voltage, which allows the control circuit to drive the main switch to 0% or 100% duty cycle as required. a change in line voltage changes the current ramp in the inductor, affecting the ramp signal, which causes the v 2 control scheme to compensate the duty cycle. since the change in the inductor current modifies the ramp signal, as in current mode control, the v 2 control scheme has the same advantages in line transient response. a change in load current will have an effect on the output voltage, altering the ramp signal. a load step immediately changes the state of the comparator output, which controls the main switch. load transient response is determined only by the comparator response time and the transition speed of the main switch. the reaction time to an output load step has no relation to the crossover frequency of the error signal loop, as in traditional control methods. the error signal loop can have a low crossover frequency, since transient response is handled by the ramp signal loop. the main purpose of this ?slow? feedback loop is to provide dc accuracy. noise immunity is significantly improved, since the error amplifier bandwidth can be rolled off at a low frequency. enhanced noise immunity improves remote sensing of the output voltage, since the noise associated with long feedback traces can be effectively filtered. line and load regulations are drastically improved because there are two independent voltage loops. a voltage mode controller relies on a change in the error signal to compensate for a derivation in either line or load voltage. this change in the error signal causes the output voltage to change corresponding to the gain of the error amplifier, which is normally specified as line and load regulation. a current mode controller maintains fixed error signal under deviation in the line voltage, since the slope of the ramp signal changes, but still relies on a change in the error signal for a deviation in load. the v 2 method of control maintains a fixed error signal for both line and load variations, since both line and load affect the ramp signal. constant frequency operation during normal operation, the oscillator generates a 200 khz, 90% duty cycle waveform. the rising edge of this waveform determines the beginning of each switching cycle, at which point the high--side switch will be turned on. the high--side switch will be turned off when the ramp signal intersects the output of the error amplifier (comp pin voltage). therefore, the switch duty cycle can be modified to regulate the output voltage to the desired value as line and load conditions change.
ncv8800 series http://onsemi.com 11 the major advantage of constant frequency operation is that the component selections, especially the magnetic component design, become very easy. oscillator frequency is fixed at 200 khz. start--up after the ncv8800 is powered up, the error amplifier will begin linearly charging the c omp pin capacitor. the comp capacitance and the source current of the error amplifier determine the slew rate of comp voltage. the output of the error amplifier is connected internally to the inverting input of the pwm comparator and it is compared with the divided down output voltage fb1/fb2 at the non--inverting input of the pwm comparator. at the beginning of each switching cycle, the oscillator output will set the pwm latch. this causes the high--side switch to turn on and the regulator output voltage to ramp up. when the divided down output voltage achieves a level set by the comp voltage, the high--side switch will be turned off. the v 2 control loop will adjust the high--side switch duty cycle as required to ensure the regulator output voltage tracks the comp voltage. since the comp voltage increases gradually, soft start can be achieved. overcurrent protection the output switch is protected on both the high side and low side. current limit is set at 1.0 a (min). figure 9. 16 lead sow (4 leads fused), ja as a function of the pad copper area (2 oz. cu. thickness), board material = 0.0625 g--10/r--4 40 70 90 100 thermal resistance, junction to ambient, r ja ,( c/w) 0 copper area (inch 2 ) 0.5 1.0 1.5 2.0 3.0 80 60 50 2.5 heat sinks a heat sink effectively increases the surface area of the package to improve the flow of heat away from the ic and into the surrounding air. each material in the heat flow path between the ic and the outside environment will have a thermal resistance. like series electrical resistances, t hese resistances are summed to determine the value of r ja : r ja = r jc + r cs + r sa (3) where: r jc = the junction--to--case thermal resistance, r cs = the case--to--heatsink thermal resistance, and r sa = the heatsink--to--ambient thermal resistance. r jc appears in the package section of the data sheet. like r ja , it too is a function of package type. r cs and r sa are functions of the package type, heatsink and the interface between them. these values appear in heat sink data sheets of heat sink manufacturers.
ncv8800 series http://onsemi.com 12 ordering information device output voltage enable option package shipping ? ncv8800sdw26 2.6 v sequenced so--16l 46 units/rail ncv8800sdw26r2 1000 tape & reel ncv8800hdw26 high voltage 46 units/rail ncv8800hdw26r2 1000 tape & reel ncv8800sdw33 3.3 v sequenced 46 units/rail ncv8800sdw33r2 1000 tape & reel ncv8800hdw33 high voltage 46 units/rail ncv8800hdw33r2 1000 tape & reel ncv8800hdw50 5.0 v high voltage 46 units/rail ncv8800hdw50r2 1000 tape & reel ncv8800hdw75 7.5 v 46 units/rail ncv8800hdw75r2 1000 tape & reel ?for information on tape and reel specificat ions, including part orientation and tape si zes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
ncv8800 series http://onsemi.com 13 package dimensions so--16l dw suffix case 751g--03 issue b d 14x b 16x seating plane s a m 0.25 b s t 16 9 8 1 h x45 _ m b m 0.25 h 8x e b a e t a1 a l c notes: 1. dimensions are in millimeters. 2. interpret dimensions and tolerances per asme y14.5m, 1994. 3. dimensions d and e do not inlcude mold protrusion. 4. maximum mold protrusion 0.15 per side. 5. dimension b does not include dambar protrusion. allowable dambar protrusion shall be 0.13 total in excess of the b dimension at maximum material condition. dim min max millimeters a 2.35 2.65 a1 0.10 0.25 b 0.35 0.49 c 0.23 0.32 d 10.15 10.45 e 7.40 7.60 e 1.27 bsc h 10.05 10.55 h 0.25 0.75 l 0.50 0.90 07 _ _ on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further noti ce to any products herein. sc illc makes no warranty, repres entation or guarantee r egarding the suitability of its produc ts for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specif ically disclaims any and all liability, including without limitation speci al, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performa nce may vary over time. all operating parameters, including ?typicals? must be validated for each cus tomer application by customer?s technical experts. scillc does not conve y any license under its patent rights nor the rights of others. scillc pr oducts are not designed, intended, or autho rized for use as components in systems i ntended for surgical implant int o the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal inj ury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, em ployees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, an y claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the p art. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800--282--9855 toll free usa/canada japan : on semiconductor, japan customer focus center 2--9--1 kamimeguro, meguro--ku, tokyo, japan 153--0051 phone : 81--3--5773--3850 ncv8800/d v 2 is a trademark of switch power, inc. literature fulfillment : literature distribution center for on semiconductor p.o. box 61312, phoenix, arizona 85082--1312 usa phone : 480--829--7710 or 800--344--3860 toll free usa/canada fax : 480--829--7709 or 800--344--3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : http://onsemi.com order literature : http://www.onsemi.com/litorder for additional information, please contact your local sales representative.

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